`timescale 1ns / 1ns

module calculation (
    input clk,
    input rst_n,
    input [3:0] a,
    input [3:0] b,
    output [8:0] c
);
    wire [8:0] mula12 = (a << 3) + (a << 2);
    wire [8:0] mulb5 = (b << 2) + b;
    reg  [8:0] out;
    reg  [8:0] prev_out;

    initial begin
        out <= 0;
        prev_out <= 0;
    end

    always @(posedge clk) begin
        if (rst_n == 0) begin
            out <= 0;
            prev_out <= 0;
        end else begin
            prev_out <= out;
            out <= mula12 + mulb5;
        end
    end
    assign c = prev_out;
endmodule
